An electronic device may perform different signal processing operations at different stages of a task. Such a device usually implements different circuit modules to carry out these different signal processing operations. Hence, a device may require many separate circuit modules.
An imaging sensor has an array of sensing pixels each producing charge carriers indicative of the amount of received radiation. The charge carriers from each pixel may be converted into an electrical pixel signal (e.g., a voltage) which is further processed by a subsequent processing circuit. Imaging sensors are becoming increasingly complex and are built with processing circuits having different circuit blocks to perform many processing operations. For example, a multiresolution sensor may have a processing circuit comprising different function blocks for summing, averaging, and analog to digital conversion.
Such a processing circuit of many circuit modules is subject to certain limitations. For example, the circuit modules occupy valuable real estate on a silicon substrate and increase the cost These and other limitations are specially problematic when the processing circuit is integrated onto the sensing array because the silicon area occupied by the processing circuit limits the space available for the photosensitive part and hence reduces the number of sensing pixels.
Therefore, it is desirable to reduce the number of circuit elements in a processing circuit capable of performing multiple signal-processing tasks.
This disclosure describes circuit architecture and associated methods for providing a special multi-task analog arithmetic circuit with a significantly reduced number of electronic elements compared to many known multi-task arithmetic circuits of the same or similar functions. This special arithmetic circuit is programmable and implements multiple circuit modules that share certain common electronic elements to reduce the number of elements. Controllable switches are provided to couple the shared common electronic elements to different circuit modules as desired. A control unit controls the switches to couple selected shared elements to form a circuit module that is activated to perform a desired arithmetic operation.
One embodiment of this special multi-task arithmetic circuit is an image processing circuit coupled to an imaging sensor array. The circuit includes a reconfigurable arithmetic circuit having a plurality of circuit elements and a plurality of switches to perform first and second arithmetic operations on pixel electrical signals from the imaging sensor array, and a control circuit coupled to control a first set of switches to couple a first set of circuit elements to form a first circuit to perform the first arithmetic operation and a second set of switches to couple at least part of the first set of circuit elements and a second set of circuit elements to form a second circuit to perform the second arithmetic operation.
Another embodiment of the special multi-task arithmetic circuit includes a sensor array of pixels to detect an input image, a reconfigurable arithmetic circuit having an array of column-parallel arithmetic cells respectively coupled to columns of the sensor array and reconfigurable to form different arithmetic circuits to perform arithmetic operations, and a control circuit coupled to the arithmetic cells and to control each arithmetic cell to perform at least addition, subtraction, multiplication, and division operations on signals from the sensor array.
The arithmetic cell includes the following elements: (1) a first signal sampling capacitor to receive the pixel signal, (2) a first switched capacitor integrator coupled to the first signal sampling capacitor, (3) a second signal sampling capacitor coupled to the first switched capacitor integrator, (4) a second switched capacitor integrator coupled to the second signal sampling capacitor, (5) a plurality of electronic switches coupled to control the sampling capacitors and the integrators and their interconnections, and (6) a plurality of communication channels having switches to couple each arithmetic cell to at least one adjacent arithmetic cell.
The communication channels may include first and second signal communication channels to provide communication between different columns. The first communication channel couples one terminal of the first signal sampling capacitor in the arithmetic cell to a corresponding terminal of a corresponding first signal sampling capacitor in the at least one adjacent arithmetic cell. The second signal communication channel couples one terminal of the second signal sampling capacitor in the arithmetic cell to a corresponding terminal of a corresponding second signal sampling capacitor in the at least one adjacent arithmetic cell.
The first switched capacitor integrator includes a signal integrating capacitor and the communication channels include a signal capacitor channel to couple one terminal of the signal integrating capacitor in the arithmetic cell to a corresponding terminal of a corresponding signal integrating capacitor in the at least one adjacent arithmetic cell.
Each pixel of the sensor array may be configured to produce a pixel signal indicative of a total of photo-induced pixel signal and non-photo-induced background signal and a pixel reset signal indicative of the non-photon-induced background signal. Accordingly, the reconfigurable arithmetic circuit may include two parallel processing channels, one for signals associated with the pixel signals and another for signals associated with the pixel reset signals of the sensor array.
These and other aspects and associated advantages of the present invention will become more apparent in light of the following detailed description, the accompanying drawings, and the claims.